In certain applications, it is advantageous to use dynamic logic circuits because they are faster than static logic circuits. Dynamic logic circuits require an internal node to be precharged to a voltage, e.g., precharged to the circuit's power supply voltage, such as to Vdd. However, in their simplest form, there is no active circuitry to hold this charge on the internal node, rather the charge is held via a capacitive charge only.
Although, dynamic logic circuits are fast, a drawback of dynamic logic circuits is that they are prone to current leakage. Consequently, a practical dynamic logic gate must use a “keeper” device that is connected to the precharged node in order to prevent diffusion leakage, source-drain leakage, gate leakage and noise from inadvertently discharging the precharged node. Any node that is not actively held at a desired state tends to drift, e.g., to Vdd, Vdd/2, or ground. If the node of a dynamic logic circuit drifts away from the precharged level, the state of the logic gate may spuriously change without input stimuli. The keeper device is a dynamic device through which enough current flows to ensure that a certain amount of leakage current does not discharge the node, while at the same time not swamping the node, so that the impact to switching speed is minimized. Additionally, it is desirable for the keeper device to have just enough strength to keep the node from discharging, while not being overly large so as to slow down, or interfere with normal switching.
In early semiconductor technologies, the keeper device provided a relatively small amount of current to compensate for leakage and was not large enough to significantly alter the speed of the dynamic logic gate. However, with advances in semiconductor technology, device geometries are decreasing. Consequently, the gate dielectrics have thinned below the tunneling range of approximately 17 angstrom and, thus, the off-state leakage of the combinatorial logic of a dynamic logic gate becomes significantly larger. As a result, there is less distinction between the off- and on-states of dynamic logic gates and, thus, there is increased sensitivity to leakage that may result in the dynamic logic gates not functioning properly. The leakage has become sufficiently large in leading-edge technology to require larger keeper devices in order to compensate for worst-case leakage. Consequently, when it comes time to discharge the node during normal operation, at which time the keeper circuit is also discharged, the nominal circuit performance of dynamic logic gates may be degraded by approximately 30%, mitigating some of dynamic logic's advantage over static logic.
For these reasons, a need exists for a current control mechanism for dynamic logic keeper circuits in an integrated circuit that will provide performance improvements of dynamic logic gates fabricated using leading-edge technologies.